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Filterless, High Efficiency, Mono 3 W Class-D Audio Amplifier SSM2319
FEATURES
Filterless Class-D amplifier with ultraefficient spreadspectrum - modulation Internal modulator synchronization (SYNC) 3 W into 3 load and 1.4 W into 8 load at 5.0 V supply with <1% total harmonic distortion (THD) 90% efficiency at 5.0 V, 1.4 W into 8 speaker Signal-to-noise ratio (SNR): 98 dB Single-supply operation: 2.5 V to 5.5 V Ultralow shutdown current: 20 nA Short-circuit and thermal protection with autorecovery Available in 9-ball, 1.5 mm x 1.5 mm WLCSP Pop-and-click suppression Built-in resistors reduce board component count Default fixed 12 dB or user-adjustable gain setting
The SSM2319 features a high efficiency, low noise modulation scheme that does not require any external LC output filters. The modulation continues to provide high efficiency even at low output power. It operates with 90% efficiency at 1.4 W into 8 or 85% efficiency at 3 W into 3 from a 5.0 V supply and has an SNR of 98 dB. Spread-spectrum pulse density modulation is used to provide lower EMI-radiated emissions compared with other Class-D architectures. SYNC can be activated in the event that end users are concerned about clock intermodulation (beating effect) of several amplifiers in close proximity. The SSM2319 has a micropower shutdown mode with a typical shutdown current of 20 nA. Shutdown is enabled by applying a logic low to the SD pin. The device also includes pop-and-click suppression circuitry. This minimizes voltage glitches at the output during turn-on and turn-off, reducing audible noise on activation and deactivation. The default gain of the SSM2319 is 12 dB, but users can reduce the gain by using a pair of external resistors (see the Gain section). The SSM2319 is specified over the industrial temperature range of -40C to +85C. It has built-in thermal shutdown and output short-circuit protection. It is available in a 9-ball, 1.5 mm x 1.5 mm wafer level chip scale package (WLCSP).
APPLICATIONS
Mobile phones MP3 players Portable gaming Portable electronics Educational toys
GENERAL DESCRIPTION
The SSM2319 is a fully integrated, high efficiency Class-D audio amplifier. It is designed to maximize performance for mobile phone applications. The application circuit requires a minimum of external components and operates from a single 2.5 V to 5.5 V supply. It is capable of delivering 3 W of continuous output power with <1% THD + N driving a 3 load from a 5.0 V supply.
FUNCTIONAL BLOCK DIAGRAM
10F 0.1F VBATT 2.5V TO 5.5V VDD OUT+ MODULATOR (-) 160k SHUTDOWN SD BIAS INTERNAL OSCILLATOR FET DRIVER OUT-
SSM2319
0.1F* AUDIO IN- AUDIO IN+ 0.1F* IN- IN+ 40k 40k
160k
POP/CLICK SUPPRESSION SYNC SYNCO SYNC OUTPUT
GND SYNCI SYNC INPUT *INPUT CAPACITORS ARE OPTIONAL IF INPUT DC COMMON-MODE VOLTAGE IS APPROXIMATELY VDD/2.
Figure 1.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2008 Analog Devices, Inc. All rights reserved.
07550-001
SSM2319 TABLE OF CONTENTS
Features .............................................................................................. 1 Applications ....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Absolute Maximum Ratings............................................................ 5 Thermal Resistance ...................................................................... 5 ESD Caution .................................................................................. 5 Pin Configuration and Function Descriptions ............................. 6 Typical Performance Characteristics ............................................. 7 Typical Application Circuits.......................................................... 12 Theory of Operation ...................................................................... 14 Overview ..................................................................................... 14 Gain .............................................................................................. 14 Pop-and-Click Suppression ...................................................... 14 Output Modulation Description .............................................. 14 Layout .......................................................................................... 15 Input Capacitor Selection .......................................................... 15 Power Supply Decoupling ......................................................... 15 Syncronization (SYNC) Operation .......................................... 15 Outline Dimensions ....................................................................... 17 Ordering Guide .......................................................................... 17
REVISION HISTORY
8/08--Revision 0: Initial Version
Rev. 0 | Page 2 of 20
SSM2319 SPECIFICATIONS
VDD = 5.0 V, TA = 25oC, RL = 8 +33 H, SYNCI = GND (standalone mode), unless otherwise noted. Table 1.
Parameter DEVICE CHARACTERISTICS Output Power Symbol POUT Conditions RL = 8 , THD = 1%, f = 1 kHz, 20 kHz BW, VDD = 5.0 V RL = 8 , THD = 1%, f = 1 kHz, 20 kHz BW, VDD = 3.6 V RL = 8 , THD = 1%, f = 1 kHz, 20 kHz BW, VDD = 2.5 V RL = 8 , THD = 10%, f = 1 kHz, 20 kHz BW, VDD = 5.0 V RL = 8 , THD = 10%, f = 1 kHz, 20 kHz BW, VDD = 3.6 V RL = 8 , THD = 10%, f = 1 kHz, 20 kHz BW, VDD = 2.5 V RL = 4 , THD = 1%, f = 1 kHz, 20 kHz BW, VDD = 5.0 V RL = 4 , THD = 1%, f = 1 kHz, 20 kHz BW, VDD = 3.6 V RL = 4 , THD = 1%, f = 1 kHz, 20 kHz BW, VDD = 2.5 V RL = 4 , THD = 10%, f = 1 kHz, 20 kHz BW, VDD = 5.0 V RL = 4 , THD = 10%, f = 1 kHz, 20 kHz BW, VDD = 3.6 V RL = 4 , THD = 10%, f = 1 kHz, 20 kHz BW, VDD = 2.5 V RL = 3 , THD = 1%, f = 1 kHz, 20 kHz BW, VDD = 5.0 V RL = 3 , THD = 1%, f = 1 kHz, 20 kHz BW, VDD = 3.6 V RL = 3 , THD = 1%, f = 1 kHz, 20 kHz BW, VDD = 2.5 V RL = 3 , THD = 10%, f = 1 kHz, 20 kHz BW, VDD = 5.0 V RL = 3 , THD = 10%, f = 1 kHz, 20 kHz BW, VDD = 3.6 V RL = 3 , THD = 10%, f = 1 kHz, 20 kHz BW, VDD = 2.5 V POUT = 1.4 W, 8 , VDD = 5.0 V POUT = 1 W into 8 , f = 1 kHz, VDD = 5.0 V POUT = 0.5 W into 8 , f = 1 kHz, VDD = 3.6 V 1.0 VCM = 2.5 V 100 mV at 217 Hz, output referred G = 12 dB Guaranteed from PSRR test VDD = 2.5 V to 5.0 V, dc input floating/ground VRIPPLE = 100 mV at 217 Hz, inputs ac GND, CIN = 0.1 F VIN = 0 V, no load, VDD = 5.0 V VIN = 0 V, no load, VDD = 3.6 V VIN = 0 V, no load, VDD = 2.5 V VIN = 0 V, load = 8 + 33 H, VDD = 5.0 V VIN = 0 V, load = 8 + 33 H, VDD = 3.6 V VIN = 0 V, load = 8 + 33 H, VDD = 2.5 V SD = GND 2.5 70 57 300 2.0 5.5 85 60 3.6 3.2 2.7 3.7 3.3 2.8 20 12 40 1.2 0.5 28 5 >100 Min Typ 1.41 0.72 0.33 1.77 0.91 0.42 2.53 1.28 0.56 3.17 1 1.6 0.72 3.11 1.52 0.68 3.71 1.9 0.85 93 0.06 0.02 VDD - 1 Max Unit W W W W W W W W W W W W W W W W W W % % % V dB kHz mV V dB dB mA mA mA mA mA mA nA dB k V V ms s k
Efficiency Total Harmonic Distortion + Noise Input Common-Mode Voltage Range Common-Mode Rejection Ratio Average Switching Frequency Differential Output Offset Voltage POWER SUPPLY Supply Voltage Range Power Supply Rejection Ratio Supply Current
THD + N VCM CMRRGSM fSW VOOS VDD PSRR PSRRGSM ISY
Shutdown Current GAIN CONTROL Closed-Loop Gain Differential Input Impedance SHUTDOWN CONTROL Input Voltage High Input Voltage Low Turn-On Time Turn-Off Time Output Impedance
ISD Av ZIN VIH VIL tWU tSD ZOUT
SD = VDD ISY 1 mA ISY 300 nA SD rising edge from GND to VDD SD falling edge from VDD to GND SD = GND
Rev. 0 | Page 3 of 20
SSM2319
Parameter NOISE PERFORMANCE Output Voltage Noise Signal-to-Noise Ratio SYNC OPERATIONAL FREQUENCY
1
Symbol en SNR
Conditions VDD = 3.6 V, f = 20 Hz to 20 kHz, inputs are ac grounded, AV = 12 dB, A weighting POUT = 1.4 W, RL = 8
Min
Typ 40 98
Max
Unit V dB MHz
5
12
Although the SSM2319 has good audio quality above 3 W, continuous output power beyond 3 W must be avoided due to device packaging limitations.
Rev. 0 | Page 4 of 20
SSM2319 ABSOLUTE MAXIMUM RATINGS
Absolute maximum ratings apply at 25C, unless otherwise noted. Table 2.
Parameter Supply Voltage Input Voltage Common-Mode Input Voltage Storage Temperature Range Operating Temperature Range Junction Temperature Range Lead Temperature (Soldering, 60 sec) ESD Susceptibility Rating 6V VDD VDD -65C to +150C -40C to +85C -65C to +165C 300C 4 kV
THERMAL RESISTANCE
JA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Table 3.
Package Type 9-Ball, 1.5 mm x 1.5 mm WLCSP PCB 1S0P 2S0P JA 162 76 JB 39 21 Unit C/W C/W
ESD CAUTION
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Rev. 0 | Page 5 of 20
SSM2319 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
BALL A1 CORNER
1 A 2 3
B
C
SSM2319
07550-002
TOP VIEW BALL SIDE DOWN (Not to Scale)
Figure 2. Pin Configuration
Table 4. Pin Function Descriptions
Pin No. 1A 1B 1C 2A 2B 2C 3A 3B 3C Mnemonic IN- IN+ GND SD SYNCI VDD SYNCO OUT- OUT+ Description Inverting Input. Noninverting Input. Ground. Shutdown Input. Active low digital input. SYNC Input. Power Supply. SYNC Output. Inverting Output. Noninverting Output.
Rev. 0 | Page 6 of 20
SSM2319 TYPICAL PERFORMANCE CHARACTERISTICS
100 RL = 8 + 33H GAIN = 12dB VDD = 2.5V VDD = 3.6V VDD = 5V 100 RL = 8 + 33H GAIN = 12dB VDD = 5V 10 10
THD + N (%)
THD + N (%)
1
1
0.1
0.1
1W 0.5W 0.25W
0.01
0.01
0.001
0.01
0.1
1
10
07550-003
10
100
1k FREQUENCY (Hz)
10k
100k
OUTPUT POWER (W)
Figure 3. THD + N vs. Output Power into RL = 8 + 33 H, Gain = 12 dB
100
Figure 6. THD + N vs. Frequency, RL = 8 + 33 H, Gain = 12 dB, VDD = 5 V
100
RL = 4 + 33H GAIN = 12dB VDD = 2.5V VDD = 3.6V VDD = 5V
RL = 4 + 33H GAIN = 12dB VDD = 5V
10
10 2W
THD + N (%)
0.1
THD + N (%)
1
1
0.1
1W 0.5W
0.01
0.01
10
100
1k FREQUENCY (Hz)
10k
100k
OUTPUT POWER (W)
Figure 4. THD + N vs. Output Power into RL = 4 + 33 H, Gain = 12 dB
100
Figure 7. THD + N vs. Frequency, RL = 4 + 33 H, Gain = 12 dB, VDD = 5 V
100
RL = 3 + 33H GAIN = 12dB VDD = 2.5V VDD = 3.6V VDD = 5V
RL = 3 + 33H GAIN = 12dB VDD = 5V
10
10
THD + N (%)
1
THD + N (%)
1
3W
0.1
1.5W 0.75W
0.1
0.01
10
100
1k FREQUENCY (Hz)
10k
100k
OUTPUT POWER (W)
Figure 5. THD + N vs. Output Power into RL = 3 + 33 H, Gain = 12 dB
Figure 8. THD + N vs. Frequency, RL = 3 + 33 H, Gain = 12 dB, VDD = 5 V
Rev. 0 | Page 7 of 20
07550-008
0.001
0.01
0.1
1
10
07550-005
0.01 0.0001
0.001
07550-007
0.001
0.01
0.1
1
10
07550-004
0.001 0.0001
0.001
07550-006
0.001 0.0001
0.001
SSM2319
100 RL = 8 + 33H GAIN = 12dB VDD = 3.6V 100 RL = 8 + 33H GAIN = 12dB VDD = 2.5V
10
10
THD + N (%)
0.1 0.5W 0.01
THD + N (%)
1
1
0.1 0.25W 0.01 0.125W 0.0625W
07550-012 07550-014 07550-013
0.25W 0.125W
07550-009
0.001
10
100
1k FREQUENCY (Hz)
10k
100k
0.001
10
100
1k FREQUENCY (Hz)
10k
100k
Figure 9. THD + N vs. Frequency, RL = 8 + 33 H, Gain = 12 dB, VDD = 3.6 V
100
Figure 12. THD + N vs. Frequency, RL = 8 + 33 H, Gain = 12 dB, VDD = 2.5 V
100
RL = 4 + 33H GAIN = 12dB VDD = 3.6V
RL = 4 + 33H GAIN = 12dB VDD = 2.5V
10
10
THD + N (%)
1W
0.1 0.5W 0.25W 0.01
THD + N (%)
1
1
0.5W
0.1 0.25W 0.125W 0.01
10
100
1k FREQUENCY (Hz)
10k
100k
07550-010
0.001
0.001
10
100
1k FREQUENCY (Hz)
10k
100k
Figure 10. THD + N vs. Frequency, RL = 4 + 33 H, Gain = 12 dB, VDD = 3.6 V
100
Figure 13. THD + N vs. Frequency, RL = 4 + 33 H, Gain = 12 dB, VDD = 2.5 V
100
RL = 3 + 33H GAIN = 12dB VDD = 3.6V 1.5W
RL = 3 + 33H GAIN = 12dB VDD = 2.5V
0.75W
10
10
THD + N (%)
THD + N (%)
1
1
0.1
0.75W 0.38W
0.1
0.38W 0.2W
0.01
0.01
10
100
1k FREQUENCY (Hz)
10k
100k
07550-011
0.001
0.001
10
100
1k FREQUENCY (Hz)
10k
100k
Figure 11. THD + N vs. Frequency, RL = 3 + 33 H, Gain = 12 dB, VDD = 3.6 V
Figure 14. THD + N vs. Frequency, RL = 3 + 33 H, Gain = 12 dB, VDD = 2.5 V
Rev. 0 | Page 8 of 20
SSM2319
3.7 RL = 8 + 33H 3.5
SUPPLY CURRENT (mA)
2.0 1.8 1.6
OUTPUT POWER (W)
RL = 8 + 33H GAIN = 12dB f = 1kHz
3.3 3.1 2.9 2.7 2.5 2.3 2.5 RL = 4 + 33H
1.4 1.2 1.0 0.8 1% 0.6 0.4 0.2 10%
RL = 3 + 33H NO LOAD
07550-015
3.0
3.5
4.0
4.5
5.0
5.5
3.0
3.5
4.0
4.5
5.0
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
Figure 15. Supply Current vs. Supply Voltage
4.0 3.5 3.0
OUTPUT POWER (W)
Figure 18. Maximum Output Power vs. Supply Voltage, RL = 8 + 33 H, Gain = 12 dB
100 90 VDD = 2.5V VDD = 5V VDD = 3.6V
DO NOT EXCEED 3W CONTINUOUS OUTPUT POWER
80 70
2.5 10% 2.0 1.5 1.0
EFFICIENCY (%)
60 50 40 30 20
1%
0.5 0 2.5
RL = 3 + 33H GAIN = 12dB f = 1kHz 3.0 3.5 4.0 4.5 5.0
07550-016
10
07550-019 07550-020
0
RL = 8 + 33H 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
SUPPLY VOLTAGE (V)
OUTPUT POWER (W)
Figure 16. Maximum Output Power vs. Supply Voltage, RL = 3 + 33 H, Gain = 12 dB
3.5 DO NOT EXCEED 3W CONTINUOUS OUTPUT POWER 3.0
Figure 19. Efficiency vs. Output Power into RL = 8 + 33 H
100 90 80 VDD = 2.5V VDD = 3.6V VDD = 5V
OUTPUT POWER (W)
2.5
EFFICIENCY (%)
70 60 50 40 30 20
2.0 1.5 1.0 0.5 0 2.5
10%
1%
RL = 4 + 33H GAIN = 12dB f = 1kHz 3.0 3.5 4.0 4.5 5.0
07550-017
10 0 RL = 4 + 33H 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 OUTPUT POWER (W)
SUPPLY VOLTAGE (V)
Figure 17. Maximum Output Power vs. Supply Voltage, RL = 4 + 33 H, Gain = 12 dB
Figure 20. Efficiency vs. Output Power into RL = 4 + 33 H
Rev. 0 | Page 9 of 20
07550-018
0 2.5
SSM2319
100 90 80 70
EFFICIENCY (%)
0.9 0.8 0.7 0.6
RL = 3 + 33H VDD = 5V
VDD = 3.6V VDD = 2.5V
VDD = 5V
POWER DISSIPATION (W)
60 50 40 30 20 10
07550-021
VDD = 3.6V 0.5 0.4 0.3 0.2 0.1 VDD = 2.5V
0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 OUTPUT POWER (W)
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
OUTPUT POWER (W)
Figure 21. Efficiency vs. Output Power into RL = 3 + 33 H
0.16 0.14
POWER DISSIPATION (W)
Figure 24. Power Dissipation vs. Output Power into RL = 3 + 33 H
450 400 350
SUPPLY CURRENT (mA)
RL = 8 + 33H
RL = 8 + 33H VDD = 5V
0.12 0.10 0.08 0.06 0.04 0.02 0 VDD = 3.6V VDD = 2.5V VDD = 5V
300 250 200 150 100 50 0
VDD = 3.6V VDD = 2.5V
07550-022
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
0.5
1.0
1.5
2.0
2.5
OUTPUT POWER (W)
OUTPUT POWER (W)
Figure 22. Power Dissipation vs. Output Power into RL = 8 + 33 H
0.30
Figure 25. Supply Current vs. Output Power into RL = 8 + 33 H
800 700
RL = 4 + 33H VDD = 5V
SUPPLY CURRENT (mA)
RL = 4 + 33H VDD = 5V
0.25
POWER DISSIPATION (W)
600 500 400 300 200 100 0 VDD = 2.5V VDD = 3.6V
0.20 VDD = 3.6V 0.15 VDD = 2.5V 0.10
0.05
07550-023
0
0.5
1.0
1.5
2.0
2.5
3.0
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
OUTPUT POWER (W)
OUTPUT POWER (W)
Figure 23. Power Dissipation vs. Output Power into RL = 4 + 33 H
Figure 26. Supply Current vs. Output Power into RL = 4 + 33 H
Rev. 0 | Page 10 of 20
07550-026
0
07550-025
0
07550-024
0
RL = 3 + 33H
0
SSM2319
900 800 700 RL = 3 + 33H VDD = 5V
7 6 5 SD INPUT OUTPUT
SUPPLY CURRENT (mA)
600 500 400 300 200 100 VDD = 2.5V
VDD = 3.6V
4
VOLTAGE (V)
07550-027
3 2 1 0 -1
07550-030 07550-031
0
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
-2 -10 -5 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 TIME (ms)
OUTPUT POWER (W)
Figure 27. Supply Current vs. Output Power into RL = 3 + 33 H
0 -10 -20 -30 7 6 5 4
Figure 30. Turn-On Response
OUTPUT
PSRR (dB)
-40 -50 -60 -70 -80 -90
07550-028
VOLTAGE (V)
3 2 1 0 -1 SD INPUT -80 -60 -40 -20 0 20 40 60 80 100
-100 10
100
1k FREQUENCY (Hz)
10k
100k
-2 -100
TIME (s)
Figure 28. Power Supply Rejection Ratio (PSRR) vs. Frequency
0 -10 -20 -30
Figure 31. Turn-Off Response
CMRR (dB)
-40 -50 -60 -70 -80 -90 100 1k FREQUENCY (Hz) 10k 100k
07550-029
-100 10
Figure 29. Common-Mode Rejection Ratio (CMRR) vs. Frequency
Rev. 0 | Page 11 of 20
SSM2319 TYPICAL APPLICATION CIRCUITS
EXTERNAL GAIN SETTINGS = 160k/(40k + REXT) 10F 0.1F VBATT 2.5V TO 5.5V VDD OUT+ MODULATOR (-) FET DRIVER OUT-
SSM2319
0.1F* AUDIO IN- AUDIO IN+ 0.1F* REXT REXT IN- IN+ 40k 40k
160k
160k SHUTDOWN SD BIAS INTERNAL OSCILLATOR
POP/CLICK SUPPRESSION SYNC SYNC OUTPUT
SYNCO
GND SYNCI
*INPUT CAPACITORS ARE OPTIONAL IF INPUT DC COMMON-MODE VOLTAGE IS APPROXIMATELY VDD/2.
Figure 32. Differential Input Configuration, User-Adjustable Gain
EXTERNAL GAIN SETTINGS = 160k/(40k + REXT ) 10F 0.1F VBATT 2.5V TO 5.5V VDD OUT+ MODULATOR (-) FET DRIVER OUT-
SSM2319
0.1F REXT REXT 0.1F IN- IN+ 40k 40k
160k
AUDIO IN+
160k SHUTDOWN SD BIAS INTERNAL OSCILLATOR GND
POP/CLICK SUPPRESSION SYNC SYNCI
07550-033
SYNCO
SYNC OUTPUT
SYNC INPUT
Figure 33. Single-Ended Input Configuration, User-Adjustable Gain
Rev. 0 | Page 12 of 20
07550-032
SYNC INPUT
SSM2319
SSM2319
STANDALONE OUT+ MODULATOR (-) FET DRIVER OUT- MODULATOR (-) FET DRIVER
SSM2319
MASTER OUT+ OUT-
SSM2319
SLAVE OUT+ MODULATOR (-) FET DRIVER OUT-
INTERNAL OSCILLATOR
SYNC SYNCI SYNC INPUT
SYNC OUTPUT SYNCO
INTERNAL OSCILLATOR
SYNC SYNCI SYNC INPUT
SYNC OUTPUT SYNCO
INTERNAL OSCILLATOR
SYNC SYNCI SYNC INPUT
SYNC OUTPUT SYNCO
TO SLAVE NOTES 1. TRACE LENGTH FROM SYNCI TO SYNCO IS LESS THAN 1mm.
FROM MASTER
Figure 34. Synchronization Operation Modes
SSM2319
MASTER OUT+ MODULATOR (-) FET DRIVER OUT-
SSM2319
SLAVE 1 OUT+ MODULATOR (-) FET DRIVER OUT-
SSM2319
SLAVE 2 OUT+ MODULATOR (-) FET DRIVER OUT-
INTERNAL OSCILLATOR
SYNC SYNCI SYNC INPUT
SYNC OUTPUT SYNCO
INTERNAL OSCILLATOR
SYNC SYNCI SYNC INPUT
SYNC OUTPUT SYNCO
INTERNAL OSCILLATOR
SYNC SYNCI SYNC INPUT
SYNC OUTPUT SYNCO
07550-036
Figure 35. Typical SYNC Master-Slave Daisy-Chain Configuration
Rev. 0 | Page 13 of 20
07550-035
SSM2319 THEORY OF OPERATION
OVERVIEW
The SSM2319 mono Class-D audio amplifier features a filterless modulation scheme that greatly reduces the external components count, conserving board space and, thus, reducing systems cost. The SSM2319 does not require an output filter. Instead, it relies on the inherent inductance of the speaker coil and the natural filtering of the speaker and human ear to fully recover the audio component of the square wave output. Most Class-D amplifiers use some variation of pulse-width modulation (PWM), but the SSM2319 uses a - modulation to determine the switching pattern of the output devices, resulting in a number of important benefits. - modulators do not produce a sharp peak with many harmonics in the AM frequency band, as pulse-width modulators often do. - modulation reduces the amplitude of spectral components at high frequencies, reducing EMI emission that may otherwise be radiated by speakers and long cable traces. Due to the inherent spread-spectrum nature of - modulation, the need for oscillator synchronization is eliminated for designs incorporating multiple SSM2319 amplifiers. The SSM2319 also offers protection circuits for overcurrent and temperature protection.
OUTPUT MODULATION DESCRIPTION
The SSM2319 uses 3-level - output modulation. Each output is able to swing from GND to VDD and vice versa. Ideally, when no input signal is present, the output differential voltage is 0 V because there is no need to generate a pulse. In a real-world situation, there are always noise sources present. Due to the constant presence of noise, a differential pulse is generated in response to this stimulus. A small amount of current flows into the inductive load when the differential pulse is generated. However, most of the time, the output differential voltage is 0 V, due to the Analog Devices, Inc., patented 3-level, - output modulation feature. This feature ensures that the current flowing through the inductive load is small. When the user wants to send an input signal, an output pulse is generated to follow the input voltage. The differential pulse density is increased by raising the input signal level. Figure 36 depicts 3-level - output modulation with and without input stimulus.
OUTPUT = 0V OUT+ OUT-
+5V 0V +5V 0V +5V 0V -5V
GAIN
The SSM2319 has a default gain of 12 dB that can be reduced by using a pair of external resistors with a value calculated as follows: External Gain Settings = 160 k/(40 k + REXT)
VOUT OUTPUT > 0V OUT+ OUT- VOUT OUTPUT < 0V OUT+ OUT- VOUT
+5V 0V +5V 0V +5V 0V
POP-AND-CLICK SUPPRESSION
Voltage transients at the output of the audio amplifiers can occur when shutdown is activated or deactivated. Voltage transients as low as 10 mV can be heard as an audio pop in the speaker. Clicks and pops can also be classified as undesirable audible transients generated by the amplifier system and, therefore, as not coming from the system input signal. Such transients can be generated when the amplifier system changes its operating mode. For example, audible transient sources include system power-up/ power-down, mute/unmute, an input source change, and a sample rate change. The SSM2319 has a pop-and-click suppression architecture that reduces these output transients, resulting in noiseless activation and deactivation.
+5V 0V +5V 0V 0V -5V
07550-034
Figure 36. 3-Level - Output Modulation With and Without Input Stimulus
Rev. 0 | Page 14 of 20
SSM2319
LAYOUT
As output power continues to increase, care must be taken to lay out PCB traces and wires properly between the amplifier, load, and power supply. A good practice is to use short, wide PCB tracks to decrease voltage drops and minimize inductance. Ensure that track widths are at least 200 mil for every inch of track length for lowest DCR and use 1 oz or 2 oz of copper PCB traces to further reduce IR drops and inductance. A poor layout increases voltage drops, consequently affecting efficiency. Use large traces for the power supply inputs and amplifier outputs to minimize losses due to parasitic trace resistance. Proper grounding guidelines help to improve audio performance, minimize crosstalk between channels, and prevent switching noise from coupling into the audio signal. To maintain high output swing and high peak output power, the PCB traces that connect the output pins to the load and to the supply pins should be as wide as possible to maintain the minimum trace resistances. It is also recommended that a large ground plane be used for minimum impedances. In addition, good PCB layouts isolate critical analog paths from sources of high interference. High frequency circuits (analog and digital) should be separated from low frequency circuits. Properly designed multilayer PCBs can reduce EMI emissions and increase immunity to the RF field by a factor of 10 or more when compared with double-sided boards. A multilayer board allows a complete layer to be used for the ground plane, whereas the ground plane side of a double-sided board is often disrupted by signal crossover. If the system has separate analog and digital ground and power planes, the analog ground plane should be underneath the analog power plane, and, similarly, the digital ground plane should be underneath the digital power plane. There should be no overlap between analog and digital ground planes or analog and digital power planes.
POWER SUPPLY DECOUPLING
To ensure high efficiency, low THD, and high PSRR, proper power supply decoupling is necessary. Noise transients on the power supply lines are short-duration voltage spikes. Although the actual switching frequency can range from 10 kHz to 100 kHz, these spikes can contain frequency components that extend into the hundreds of megahertz. The power supply input needs to be decoupled with a good quality, low ESL, low ESR capacitor, usually of around 4.7 F. This capacitor bypasses low frequency noises to the ground plane. For high frequency transients noises, use a 0.1 F capacitor as close as possible to the VDD pin of the device. Placing the decoupling capacitor as close as possible to the SSM2319 helps to maintain efficient performance.
SYNCRONIZATION (SYNC) OPERATION
SYNC is the feature that allows an external clock signal to control the modulator of the SSM2319. The SSM2319 can act in standalone mode, act as a master device, or act as a slave device. Although the inherent random switching frequency of the Analog Devices patented 3-level PDM modulation virtually eliminates the need for SYNC, this feature can be activated in the event that end users are concerned about clock intermodulation (beating effect) of several amplifiers in close proximity. Another use for the SYNC feature is its ability to adjust modulator frequency to move harmonic interference to a less sensitive frequency band in certain applications with very delicate interference requirements. Although the synchronization frequency operates from 5 MHz to 12 MHz, the optimal operating range is 6 MHz to 9 MHz. Modulator synchronization is initiated after the internal shutdown signal is released. SYNCO buffers the internal oscillator clock with a delay of 127 clock cycles. When synchronizing several SSM2319 amplifiers, configure them in a daisy-chain configuration, as shown in Figure 35. Using this configuration causes a small delay in the SYNCO-toSYNCO transitions of multiple SSM2319s, preventing large surges of instantaneous current and reducing excessive loading of the power supply. When configuring one device to act as a master device, it is mandatory that the connection from SYNCO to SYCNI be less than 1 mm. As in many digital systems, to maintain signal integrity when interfacing several clocking systems, users must insert series dumping resistors close to the SYNCO pin if long trace lengths are used for synchronization connections. A typical value used is 750 . The series dumping resistor should be placed as close to the SYNCO pin as possible. If careful layout practices are followed to minimize signal trace routing from the SYNCO pin of one device to the SYNCI pin of another, a dumping resistor is not necessary. If the SYNC feature is not used, or if the SYNC feature is not interfacing the SYNCO pin to an external device, it is recommended that the SYNCO pin be floated.
INPUT CAPACITOR SELECTION
The SSM2319 does not require input coupling capacitors if the input signal is biased from 1.0 V to VDD - 1.0 V. Input capacitors are required if the input signal is not biased within this recommended input dc common-mode voltage range, if high-pass filtering is needed, or if using a single-ended source. If highpass filtering is needed at the input, the input capacitor, along with the input resistor of the SSM2319, form a high-pass filter whose corner frequency is determined by fC = 1/{2 x (40 k + REXT) x CIN} The input capacitor can significantly affect the performance of the circuit. Not using input capacitors degrades both the output offset of the amplifier and the PSRR performance.
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SSM2319
Operating Modes
The SYNC operating modes include the following: * Initial SYNC startup. An internal reference signal, REF, is released after one complete internal clock cycle (MCLK). After REF is released, another internal signal, MOD, waits 127 internal clock cycles. This operates as a training signal to determine the SYNCI/SYNCO connection. During this time, SYNCO is the internal clock signal. SYNCI = GND or VDD. SYNCO stops generating pulses. The modulator is controlled by an internal clock signal, as shown in Figure 37.
SD INTERNAL SIGNAL MOD REF
*
SYNCI = external clock. SYNCO is a buffered clock output sourced from an external clock signal. One clock cycle after the internal modulator detect signal is released, an irregular pulse appears on MCLK before the first buffered output signal begins on SYNCO, as shown in Figure 39.
SD INTERNAL REF SIGNAL MOD
*
SYNCI SYNCO MCLK SYNCI = CLKIN
07550-039
07550-041
CLK LOSS DETECT
Figure 39. SYNCI = External Clock
*
SYNCI SYNCO MCLK SYNCI = GND
07550-037
SYNCI = GND, transitions to clock. When the SYNCI pin is connected to GND first but then transitions to a clock signal, SYNCO generates several internal clock signals before finally being synchronized to the external clock signal, as shown in Figure 40.
SD INTERNAL REF SIGNAL MOD SYNCI
Figure 37. SYNCI = GND or VDD
*
SYNCI = SYNCO. SYNCO is the delayed clock signal of SYNCI, as shown in Figure 38.
SD INTERNAL REF SIGNAL MOD
MCLK SYNCI = GND TO CLKIN
Figure 40. SYNCI = GND to Clock Input
SYNCI SYNCO MCLK SYNCI = SYNCO
07550-038
*
Figure 38. SYNCI = SYNCO
SYNCI = CLK, transitions to GND. When SYNCI is connected to a clock signal but then transitions to GND, the SYNCO pin immediately stops generating a clock signal. After a short clock loss detect time, the internal modulator synchronizes to the internal clock signal, as shown in Figure 41.
SD INTERNAL REF SIGNAL MOD
SYNCI SYNCO MCLK SYNCI = CLKIN TO GND
Figure 41. SYNCI = Clock Input to GND
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07550-040
SYNCO
SSM2319 OUTLINE DIMENSIONS
1.490 1.460 SQ 1.430 0.655 0.600 0.545 SEATING PLANE 0.350 0.320 0.290
3 2 1 A
A1 BALL CORNER
B
0.50 BALL PITCH TOP VIEW
(BALL SIDE DOWN)
C
0.385 0.360 0.335
BOTTOM VIEW 0.270 0.240 0.210
(BALL SIDE UP)
Figure 42. 9-Ball Wafer Level Chip Scale Package [WLCSP] (CB-9-2) Dimensions shown in millimeters
ORDERING GUIDE
Model SSM2319CBZ-R2 1 SSM2319CBZ-REEL1 SSM2319CBZ-REEL71 EVAL-SSM2319Z1
1
Temperature Range -40C to +85C -40C to +85C -40C to +85C
Package Description 9-Ball Wafer Level Chip Scale Package [WLCSP] 9-Ball Wafer Level Chip Scale Package [WLCSP] 9-Ball Wafer Level Chip Scale Package [WLCSP] Evaluation Board
101507-C
Package Option CB-9-2 CB-9-2 CB-9-2
Z = RoHS Compliant Part.
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SSM2319 NOTES
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SSM2319 NOTES
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SSM2319 NOTES
(c)2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07550-0-8/08(0)
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